The present invention relates to a method of manufacturing semiconductor devices with accurately formed sub-micron features. The present invention has particular applicability in manufacturing high density, multi-level flash-memory semiconductor devices with reliable, low resistance contacts/vias.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet semiconductor devices exhibiting the requisite reliability and circuit speed. Implementation becomes particularly problematic in manufacturing flash memory devices having a design rule less than about 0.15 micron and under, e.g., less than about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate in which various elements are formed, such as transistors, and a plurality of overlying sequentially formed interlayer dielectrics and conductive patterns in which an interconnect system is formed comprising conductive lines. Typically, conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive level comprising at least one conductive feature, forming in an opening through the ILD by conventional photolithographic and etching techniques and filling the opening with a conductive material. Excess conductive material or the overburden on the surface ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known damascene and basically involve forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with an upper conductive line.
As geometries proceed into the deep sub-micron regime, the formation of reliable, low resistance contacts and interconnects becomes particularly problematic. For example, as contact/via openings are reduced in diameter and the aspect ratio (depth/diameter) increased, the openings become more vulnerable to defects, such as seams and coring in the form of porosity running through the central portion of the contact or via. Such seams and coring undesirably result in high and unstable contact resistance distribution.
Accordingly, there exists a need for methodology enabling the manufacture of semiconductor devices with improved reliability, including semiconductor devices containing MOS transistors as well as flash memory devices, such as electrically erasable programmable read only memory (EEPROM) devices. There exists a particular need for methodology enabling the manufacture of semiconductor devices having features in the deep sub-micron range and containing reliable and low resistance contacts and vias.
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability.
Another advantage of the present invention is a method of manufacturing a semiconductor device having features in the deep sub-micron regime with highly reliability vias and contacts exhibiting low and stable contact resistance distribution.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming an opening extending into a dielectric layer from and having edges at the main surface of the dielectric layer; sputter etching to remove dielectric material from the dielectric layer and flare the edges of the opening such that they are tapered at an angle less than 90xc2x0 from the main surface of the dielectric layer; depositing a barrier layer lining the opening; and depositing tungsten (W) at a deposition rate of about 1,900 to about 2,300 xc3x85/min.
Embodiments of the present invention comprise forming an opening in an oxide dielectric layer, such as a boron-phosphorus-doped silicated glass (BPSG) or a composite oxide layer comprising a BPSG layer with a silicon oxide layer derived from tetraethyl orthosilicate (TEOS) thereon, sputter etching to remove about 180 xc3x85 to about 230 xc3x85 of material from the oxide layer, thereby tapering the edges of the opening so that they are inclined at an angle of about 83xc2x0 to about 86xc2x0 with respect to the main surface of the dielectric layer, depositing an initial barrier layer of titanium (Ti) and then depositing at least one layer, e.g., three layers, of titanium nitride on the titanium layer. The opening is then filled with W at the low deposition rate and at a relatively low temperature, e.g., from about 400xc2x0 C. to about 430xc2x0 C.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description wherein the embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.